The need for system integration led to the development of circuit techniques tailored to standard technologies--for example NMOS or CMOS technology--suitable for very large scale integration (VLSI). A technology-specific circuit method of this type is, for example, SC (switched capacitor) technology, with which PCM converters, discrete-time filters such as digital filters and programmable SC filters, A/D converters and continuous-time filters can be produced.
The circuits using SC technology are, in the case of capacitors and resistors, distributed elements, with parasitic capacitances and resistances being generated additionally.
For example, it was found that the gain in the case of an SC filter implemented with an n-tub CMOS process was subject to severe fluctuation during prober measurement of wafers, and that it was immaterial here whether the wafers were provided with a protective layer or uncovered. The causes for this were found to be surface leakage currents of 10 pA that can form as a result of the surface being altered by water absorption.
In addition, parasitic capacitances connected by the surface leakage currents are formed in the wafers provided with a protective layer.
A situation of this type is shown in FIGS. 1a and 1b, which each show a diagrammatic cross-sectional view of a MOS semiconductor array, where in each case two circuit paths 7a and 7b are mounted on a field oxide layer 2 generated in a semiconductor element 1 and comprise aluminum. The array in FIG. 1b is additionally covered by a protective layer 8, for example of silicon dioxide (SiO.sub.2). Semiconductor wafers not provided with a protective layer in accordance with FIG. 1a are manufactured particularly in the development stage of a circuit. By contrast, in series production the semiconductor wafers in accordance with FIG. 1b are passivated with a protective layer, which serves first and foremost as protection against scratches.
After manufacture of the semiconductor wafers having MOS semiconductor arrays in accordance with FIGS. 1a and 1b, water collects on the hydrophilic oxide surface 9 between the circuit paths 7a and 7b or on the hydrophilic SiO.sub.2 surface 10 of the protective layer 8, with the result that surface leakage currents form. The leakage current paths are shown in FIGS. 1a and 1b as dashed lines. In addition, the dielectric properties of the protective layer 8 lead to the formation of parasitic capacitances, identified in FIG. 1b as C1 and C2. These parasitic capacitances may have a disturbing effect particularly at low frequencies of, for example, 175 Hz, which leads in series production to high losses in the circuit yield because of non-reproducible measuring results during prober measurement. Prober measurement is however necessary, as otherwise defective chips are built up and manufacturing costs are too high.